Assura Layout Vs. Schematic Verifier

Assura™ Layout vs. Schematic (LVS) verifier is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura LVS ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout. By automatically extracting devices and nets formed across layout hierarchy and comparing them to the schematic netlist, Assura LVS provides fast, efficient verification in both interactive and batch mode.

As part of the Virtuoso custom design platform, Assura LVS enables design teams to check, identify, and correct layout connectivity and physical and logical mismatch errors to achieve design sign-off before tapeout. With a GUI-guided debugging environment and hierarchical processing techniques, Assura LVS reduces the overall verification cycle time, especially for designs with high complexity and many levels of layout hierarchy. Assura LVS, along with Assura DRC and Assura RCX, provides the best choice for doing fast and accurate silicon analysis of your custom designs.

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