Incisive Mixed Language Simulator

Simulation is the core of the Cadence® Incisive® functional verification platform. With native mixed-language support, dynamic assertion checking, transaction-level support, HDL analysis, and a complete debug environment, Incisive simulation verifies nanometer-scale ICs with speed and efficiency. Tailored to your needs, the Incisive platform offers three simulators: the HDL Simulator for basic RTL simulation; the Design Team Simulator for full multi-language design, including SystemVerilog; and the Enterprise Specman® Simulator for complex system development and verification.

Part of the Incisive HDL family of products, the entry-level HDL Simulator supports RTL simulation for both Verilog and VHDL. Its SystemVerilog support includes the design constructs routinely used by design engineers. It also offers integrated code coverage and a powerful graphical debug environment.

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