Cadence SoC Encounter
A configuration of the Cadence® Encounter® digital IC design platform, the SoC Encounter™ RTL-to-GDSII system supports complex hierarchical designs of more than 100M gates. It combines advanced RTL synthesis, silicon virtual prototyping, clock mesh synthesis, design for yield, mixed-signal support, dataflow-driven macro placement, and nanometer routing. It also includes the latest low-power and yield capabilities that are critical for advanced 65nm designs. The SoC Encounter system combines RTL synthesis, silicon virtual prototyping, and full-chip implementation in a single system. It is optimized to support high performance 65nm designs. It enables engineers to synthesize to a flat virtual prototype implementation—including full-chip, routed wires—right at the beginning of the design cycle.
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